1. Field of the Invention
The present invention relates to a register address specifying circuit and a data processor comprising the same. More particularly, it relates to a data processor which accesses two register contents at the same time by comprising the register address specifying circuit capable of, besides accessing a specifying address register, accessing also a register whose address is one address different from the specified register address, when executing the instruction for transferring a plurality of register contents.
2. Description of the Related Art
Conventionally, in a data processor, for the purpose of accessing data used frequently at a high speed with a simple mechanism, a register file comprising about 16 general purpose registers is provided and the data being accessed frequently and the intermediate operation results are held in the register file.
In softwares using such register file, a technique for permuting data in the register file at borders of a series of processings is employed. Accordingly, processing for storing the data from the registers to a memory by several numbers continuously at a time, or processings for loading the data from the memory to the registers by several numbers continuously at a time are repeated frequently.
In high-level languages such as the C or the Pascal, a technique of rearranging frequently used variables into the registers at every procedure is used often. Accordingly, in the softwares designed in these high-level languages, it is often the case that a plurality of data are stored to the memory from the registers, or conversely, a plurality of data are loaded to the registers from the memory.
Therefore, a data processor having a multi-data transfer instruction which stores a plurality of data into the memory from the registers by one instruction, or loads a plurality of data to the registers from the memory by one instruction has been proposed hitherto. In such a multi-data transfer instruction, a technique of indicating the register, to which data is to be transferred, by a register list corresponding to a bit string of "0" and "1" is used. Accordingly, it is necessary to search the register list and encode a register number to be transferred at a high speed, therefore, for this purpose an encoding circuit called a priority encoder is proposed as a hardware.
When executing the multi-data transferring instruction, data were transferred by decoding the register number outputted from the priority encoder and accessing the registers sequentially. Accordingly, even when transferring the register contents of serial register numbers, it is arranged such that the register numbers are decoded one by one, and the register address specifying circuit cannot access the register whose number is next to the inputted number.
In the conventional register address specifying circuit, an inputted register number and the register to be accessed thereby is corresponded with each other at one against one. Therefore, in the case where the register number inputted and the register whose register number adjacent thereto are accessed, the register number being inputted to the register number specifying circuit must be incremented or decremented. Also, such increment or decrement must be carried out by hardwares such as a counter, so that in the case where the inputted register number and the register adjacent thereto must by accessed at the same time, a delay time may be prolonged.
In the conventional data processor, when the plural data transferring instruction is executed, data are transferred by accessing the registers one by one sequentially according to the register number obtained by searching a register list using the priority encoder and encoding the bit position of "1" (or "0") as a binary digit. Accordingly, the transferring operation must be repeated at least the same number of data to be transferred.